The demand for reduction in size and an increase in density of electronic components has driven the industry to produce smaller and more complex integrated circuits (IC). These trends have also forced the development of IC packages having smaller footprints, higher lead counts, and better electrical and thermal performance. At the same time, these IC packages are required to meet accepted industry standards both for reliability and in form factors acceptable to the end user. Automated pick and place equipment of the end user requires robust standardized package form factors, such as that of molded plastic packages which have been familiar to the industry.
In response to these issues the semiconductor industry has developed a number of different packages having an integrated circuit electrically connected to one surface of a substrate and an array of solder balls protruding from the opposite major surface of the substrate. In the broadest sense, the packages are referred to as ball grid array (BGA) packages. The solder balls provide mechanical and electrical interconnection to the printed circuit board (PCB) or other form of external circuitry. Generally, the packages have a relatively small footprint due to contacts under the package rather than having leads extending from the package sides, and have lower inductance as a result of the wide, short ball contacts.
One type of BGA package makes use of a somewhat rigid laminate substrate which is not unlike the materials and conductors used in PCB technology. Often these package substrates have multiple dielectric and conductor layers and have been used with large chip sizes and high pin count devices, but have found limited wide spread acceptance because the low interconnection density on the substrate results in a larger than desired package size.
Another solder ball connected package is a chip scale package (CSP) wherein the footprint of the package is no more than 20 percent greater than the chip size. This type of device frequently includes photopatterned interconnections on a flexible dielectric film interposer which in turn allows a smaller package footprint. However, because chip sizes have decreased and the number of input/output connections has increased, these packages are limited in application to low pin count circuits. Moreover, because the footprint of the solder ball contacts and the package size are directly associated with the chip, standardization which is so important to the industry is not possible.
A near CSP device, shown in FIG. 1, includes a flexible tape interposer 11 with a semiconductor chip 10 having bond wires 15 connected to the first surface 111 of the interposer 11 and solder balls 13 attached to the second surface 112 of the interposer 11. The back side of the chip is attached to the interposer by a chip attach adhesive 14 equal to or slightly larger in area than that of the chip. A molded thermosetting polymer 12 encapsulates the chip 10, wire bonds 15, and top surface 111 of the interposer.
This over molded tape carrier package (TCP) satisfies the need for low cost assembly, high density patterned interconnections on the interposer, and a molded body which can meet industry standards. Further, this package allows for a variety of different chip sizes within the same package form factor. However, the device has suffered from less than optimum solder joint reliability which has restricted its temperature cycling capability. Solder connections in close proximity to both the rigid, low thermal expansion silicon chip 10 and the higher expansion plastic molded body 12 are subject to cracks 213 or intermittent failures after soldering the package 12 to a relatively high expansion printed circuit board 26, as shown in FIG. 2. As the PCB 26 goes through thermal excursions, high levels of stress are placed on the solder joints in close proximity to the chip edges 210, and in turn, the stresses may result in cracks 213 at the solder ball interfaces to PCB or interposer. The relatively thin interposer 211, typically in the range of 25 to 150 microns thick, offers little buffering from thermally induced stresses or from impact initiated mechanical stresses. Solder joints completely under the chip or those completely under the molded plastic body are subject to less stress as a result of PCB thermal excursions than those near the chip edges where multiple stresses are concentrated.
Thermal and mechanical stresses in semiconductor packages have been the subject of studies for years, and manufacturers consider the interactions of thickness, elastic modulus, and thermal expansion of dissimilar materials against manufacturing and other trade-offs in an attempt to avoid damage to components, particularly interfaces which are brittle and/or have low strength.
There is a need in the industry for a robust, reliable small outline package having low inductance as offered by solder ball contacts, a manufacturing technology compatible with high volume and low cost processing, and a user friendly package outline. However, it is also desirable that the package be able to meet reliability and testing needs over the full range of environmental conditions as established by the industry.